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root/bsp/hal/ppc/prep/interrupt.c

DEFINITIONS

1. update_mask
2. interrupt_unmask
3. interrupt_mask
4. interrupt_setup
5. interrupt_lookup
6. interrupt_handler
7. interrupt_init

   1 /*-
   2  * Copyright (c) 2009, Kohsuke Ohtani
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. Neither the name of the author nor the names of any co-contributors
  14  *    may be used to endorse or promote products derived from this software
  15  *    without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  */
  30 /*
  31  * interrupt.c - interrupt management routines for intel 8259 chip
  32  */
  34 #include <kernel.h>
  35 #include <hal.h>
  36 #include <irq.h>
  37 #include <io.h>
  38 #include <cpufunc.h>
  39 #include <context.h>
  40 #include <trap.h>
  41 #include <clock.h>
  42 #include <locore.h>
  43 #include <sys/ipl.h>
  45 /* Number of IRQ lines */
  46 #define NIRQS           16
  48 /* I/O address for master/slave programmable interrupt controller */
  49 #define PIC_M           0x20
  50 #define PIC_S           0xa0
  52 /* Edge/level control register */
  53 #define ELCR            0x4d0
  55 /*
  56  * Interrupt priority level
  57  *
  58  * Each interrupt has its logical priority level, with 0 being
  59  * the highest priority. While some ISR is running, all lower
  60  * priority interrupts are masked off.
  61  */
  62 static volatile int irq_level;
  64 /*
  65  * Interrupt mapping table
  66  */
  67 static int      ipl_table[NIRQS];       /* Vector -> level */
  68 static u_int    mask_table[NIPLS];      /* Level -> mask */
  70 /*
  71  * Set mask for current ipl
  72  */
  73 static void
update_mask(void)
  75 {
u_int mask = mask_table[irq_level];
outb(PIC_M + 1, mask & 0xff);
outb(PIC_S + 1, mask >> 8);
  80 }
  82 /*
  83  * Unmask interrupt in PIC for specified irq.
  84  * The interrupt mask table is also updated.
  85  * Assumed CPU interrupt is disabled in caller.
  86  */
  87 void
interrupt_unmask(int vector, int level)
  89 {
u_int unmask = (u_int)~(1 << vector);
  91         int i, s;
s = splhigh();
ipl_table[vector] = level;
  95         /*
  96          * Unmask target interrupt for all
  97          * lower interrupt levels.
  98          */
  99         for (i = 0; i < level; i++)
mask_table[i] &= unmask;
update_mask();
splx(s);
 103 }
 105 /*
 106  * Mask interrupt in PIC for specified irq.
 107  * Interrupt must be disabled when this routine is called.
 108  */
 109 void
interrupt_mask(int vector)
 111 {
u_int mask = (u_int)(1 << vector);
 113         int i, level, s;
s = splhigh();
level = ipl_table[vector];
 117         for (i = 0; i < level; i++)
mask_table[i] |= mask;
ipl_table[vector] = IPL_NONE;
update_mask();
splx(s);
 122 }
 124 /*
 125  * Setup interrupt mode.
 126  * Select whether an interrupt trigger is edge or level.
 127  */
 128 void
interrupt_setup(int vector, int mode)
 130 {
 131         int port, s;
u_int bit;
u_char val;
s = splhigh();
port = vector < 8 ? ELCR : ELCR + 1;
bit = (u_int)(1 << (vector & 7));
val = inb(port);
 140         if (mode == IMODE_LEVEL)
val |= bit;
 142         else
val &= ~bit;
outb(port, val);
splx(s);
 146 }
 148 /*
 149  * Get interrupt source.
 150  */
 151 static int
interrupt_lookup(void)
 153 {
 154         int irq;
outb(PIC_M, 0x0c);      /* poll and ack */
irq = inb(PIC_M) & 7;
 158         if (irq == 2) {
outb(PIC_S, 0x0c);
irq = (inb(PIC_M) & 7) + 8;
 161         }
 162         return irq;
 163 }
 165 /*
 166  * Common interrupt handler.
 167  *
 168  * This routine is called from the low level interrupt routine
 169  * written in assemble code. The interrupt flag is automatically
 170  * disabled by h/w in CPU when the interrupt is occurred. The
 171  * target interrupt will be masked in ICU while the irq handler
 172  * is called.
 173  */
 174 void
 175 interrupt_handler(struct cpu_regs *regs)
 176 {
 177         int vector;
 178         int old_ipl, new_ipl;
 180         /* Handle decrementer interrupt */
 181         if (regs->trap_no == TRAP_DECREMENTER) {
clock_isr(NULL);
 183                 return;
 184         }
 186         /* Find pending interrupt */
vector = interrupt_lookup();
 189         /* Adjust interrupt level */
old_ipl = irq_level;
new_ipl = ipl_table[vector];
 192         if (new_ipl > old_ipl)          /* Ignore spurious interrupt */
irq_level = new_ipl;
update_mask();
 196         /* Dispatch interrupt */
splon();
irq_handler(vector);
sploff();
 201         /* Restore interrupt level */
irq_level = old_ipl;
update_mask();
 204 }
 206 /*
 207  * Initialize 8259 interrupt controllers.
 208  * All interrupts will be masked off in ICU.
 209  */
 210 void
interrupt_init(void)
 212 {
 213         int i;
irq_level = IPL_NONE;
 217         for (i = 0; i < NIRQS; i++)
ipl_table[i] = IPL_NONE;
 220         for (i = 0; i < NIPLS; i++)
mask_table[i] = 0xfffb;
outb(PIC_M, 0x11);      /* Start initialization edge, master */
outb(PIC_M + 1, 0x00);  /* Set h/w vector = 0x0 */
outb(PIC_M + 1, 0x04);  /* Chain to slave (IRQ2) */
outb(PIC_M + 1, 0x01);  /* 8086 mode */
outb(PIC_S, 0x11);      /* Start initialization edge, master */
outb(PIC_S + 1, 0x08);  /* Set h/w vector = 0x8 */
outb(PIC_S + 1, 0x02);  /* Slave (cascade) */
outb(PIC_S + 1, 0x01);  /* 8086 mode */
outb(PIC_S, 0x0b);      /* Read ISR by default */
outb(PIC_M, 0x0b);      /* Read ISR by default */
outb(PIC_S + 1, 0xff);  /* Mask all */
outb(PIC_M + 1, 0xfb);  /* Mask all except IRQ2 (cascade) */
 238 }