PIC_M 78 bsp/hal/ppc/prep/interrupt.c outb(PIC_M + 1, mask & 0xff); PIC_M 156 bsp/hal/ppc/prep/interrupt.c outb(PIC_M, 0x0c); /* poll and ack */ PIC_M 157 bsp/hal/ppc/prep/interrupt.c irq = inb(PIC_M) & 7; PIC_M 160 bsp/hal/ppc/prep/interrupt.c irq = (inb(PIC_M) & 7) + 8; PIC_M 223 bsp/hal/ppc/prep/interrupt.c outb(PIC_M, 0x11); /* Start initialization edge, master */ PIC_M 224 bsp/hal/ppc/prep/interrupt.c outb(PIC_M + 1, 0x00); /* Set h/w vector = 0x0 */ PIC_M 225 bsp/hal/ppc/prep/interrupt.c outb(PIC_M + 1, 0x04); /* Chain to slave (IRQ2) */ PIC_M 226 bsp/hal/ppc/prep/interrupt.c outb(PIC_M + 1, 0x01); /* 8086 mode */ PIC_M 234 bsp/hal/ppc/prep/interrupt.c outb(PIC_M, 0x0b); /* Read ISR by default */ PIC_M 237 bsp/hal/ppc/prep/interrupt.c outb(PIC_M + 1, 0xfb); /* Mask all except IRQ2 (cascade) */ PIC_M 76 bsp/hal/x86/pc/interrupt.c outb(PIC_M + 1, mask & 0xff); PIC_M 171 bsp/hal/x86/pc/interrupt.c outb(PIC_M, 0x20); /* Non specific EOI to master */ PIC_M 200 bsp/hal/x86/pc/interrupt.c outb_p(PIC_M, 0x11); /* Start initialization edge, master */ PIC_M 201 bsp/hal/x86/pc/interrupt.c outb_p(PIC_M + 1, 0x20); /* Set h/w vector = 0x20 */ PIC_M 202 bsp/hal/x86/pc/interrupt.c outb_p(PIC_M + 1, 0x04); /* Chain to slave (IRQ2) */ PIC_M 203 bsp/hal/x86/pc/interrupt.c outb_p(PIC_M + 1, 0x01); /* 8086 mode */ PIC_M 211 bsp/hal/x86/pc/interrupt.c outb(PIC_M + 1, 0xfb); /* Mask all except IRQ2 (cascade) */