PIC_S              79 bsp/hal/ppc/prep/interrupt.c 	outb(PIC_S + 1, mask >> 8);
PIC_S             159 bsp/hal/ppc/prep/interrupt.c 		outb(PIC_S, 0x0c);
PIC_S             228 bsp/hal/ppc/prep/interrupt.c 	outb(PIC_S, 0x11);	/* Start initialization edge, master */
PIC_S             229 bsp/hal/ppc/prep/interrupt.c 	outb(PIC_S + 1, 0x08);	/* Set h/w vector = 0x8 */
PIC_S             230 bsp/hal/ppc/prep/interrupt.c 	outb(PIC_S + 1, 0x02);	/* Slave (cascade) */
PIC_S             231 bsp/hal/ppc/prep/interrupt.c 	outb(PIC_S + 1, 0x01);	/* 8086 mode */
PIC_S             233 bsp/hal/ppc/prep/interrupt.c 	outb(PIC_S, 0x0b);	/* Read ISR by default */
PIC_S             236 bsp/hal/ppc/prep/interrupt.c 	outb(PIC_S + 1, 0xff);	/* Mask all */
PIC_S              77 bsp/hal/x86/pc/interrupt.c 	outb(PIC_S + 1, mask >> 8);
PIC_S             170 bsp/hal/x86/pc/interrupt.c 		outb(PIC_S, 0x20);	/* Non specific EOI to slave */
PIC_S             205 bsp/hal/x86/pc/interrupt.c 	outb_p(PIC_S, 0x11);		/* Start initialization edge, master */
PIC_S             206 bsp/hal/x86/pc/interrupt.c 	outb_p(PIC_S + 1, 0x28);	/* Set h/w vector = 0x28 */
PIC_S             207 bsp/hal/x86/pc/interrupt.c 	outb_p(PIC_S + 1, 0x02);	/* Slave (cascade) */
PIC_S             208 bsp/hal/x86/pc/interrupt.c 	outb_p(PIC_S + 1, 0x01);	/* 8086 mode */
PIC_S             210 bsp/hal/x86/pc/interrupt.c 	outb(PIC_S + 1, 0xff);		/* Mask all */