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root/bsp/boot/ppc/prep/debug.c/* [<][>][^][v][top][bottom][index][help] */DEFINITIONSThis source file includes following definitions.1 /*- 2 * Copyright (c) 2009, Kohsuke Ohtani 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <boot.h> 32 33 34 #define SCREEN_80x25 1 35 /* #define SCREEN_80x50 1 */ 36 37 #define COM_BASE CONFIG_NS16550_BASE 38 39 /* Register offsets */ 40 #define COM_RBR (COM_BASE + 0x00) /* receive buffer register */ 41 #define COM_THR (COM_BASE + 0x00) /* transmit holding register */ 42 #define COM_IER (COM_BASE + 0x01) /* interrupt enable register */ 43 #define COM_FCR (COM_BASE + 0x02) /* FIFO control register */ 44 #define COM_IIR (COM_BASE + 0x02) /* interrupt identification register */ 45 #define COM_LCR (COM_BASE + 0x03) /* line control register */ 46 #define COM_MCR (COM_BASE + 0x04) /* modem control register */ 47 #define COM_LSR (COM_BASE + 0x05) /* line status register */ 48 #define COM_MSR (COM_BASE + 0x06) /* modem status register */ 49 #define COM_DLL (COM_BASE + 0x00) /* divisor latch LSB (LCR[7] = 1) */ 50 #define COM_DLM (COM_BASE + 0x01) /* divisor latch MSB (LCR[7] = 1) */ 51 52 #ifdef DEBUG 53 volatile u_char *ISA_io = (u_char *)0x80000000; 54 55 static void 56 outb(int port, u_char val) 57 { 58 59 ISA_io[port] = val; 60 } 61 62 static u_char 63 inb(int port) 64 { 65 66 return (ISA_io[port]); 67 } 68 #endif 69 70 /* 71 * Print one chracter 72 */ 73 void 74 debug_putc(int c) 75 { 76 77 #if defined(DEBUG) && defined(CONFIG_DIAG_SERIAL) 78 /* 79 * output to serial port. 80 */ 81 while (!(inb(COM_LSR) & 0x20)) 82 ; 83 outb(COM_THR, (u_char)c); 84 #endif 85 86 #if defined(DEBUG) && defined(CONFIG_DIAG_QEMU) 87 inb(0xf00); /* dummy */ 88 outb(0xf00, (u_char)c); 89 #endif 90 } 91 92 /* 93 * Initialize debug port. 94 */ 95 void 96 debug_init(void) 97 { 98 99 #if defined(DEBUG) && defined(CONFIG_DIAG_SERIAL) 100 /* 101 * Initialize serial port. 102 */ 103 if (inb(COM_LSR) == 0xff) 104 return; /* Serial port is disabled */ 105 106 outb(COM_IER, 0x00); /* Disable interrupt */ 107 outb(COM_LCR, 0x80); /* Access baud rate */ 108 outb(COM_DLL, 0x01); /* 115200 baud */ 109 outb(COM_DLM, 0x00); 110 outb(COM_LCR, 0x03); /* N, 8, 1 */ 111 outb(COM_MCR, 0x03); /* Ready */ 112 outb(COM_FCR, 0x00); /* Disable FIFO */ 113 inb(COM_RBR); 114 inb(COM_RBR); 115 #endif 116 } /* [<][>][^][v][top][bottom][index][help] */ | |||
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Copyright© 2005-2009 Kohsuke Ohtani |
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