outb 83 bsp/boot/ppc/prep/debug.c outb(COM_THR, (u_char)c); outb 88 bsp/boot/ppc/prep/debug.c outb(0xf00, (u_char)c); outb 106 bsp/boot/ppc/prep/debug.c outb(COM_IER, 0x00); /* Disable interrupt */ outb 107 bsp/boot/ppc/prep/debug.c outb(COM_LCR, 0x80); /* Access baud rate */ outb 108 bsp/boot/ppc/prep/debug.c outb(COM_DLL, 0x01); /* 115200 baud */ outb 109 bsp/boot/ppc/prep/debug.c outb(COM_DLM, 0x00); outb 110 bsp/boot/ppc/prep/debug.c outb(COM_LCR, 0x03); /* N, 8, 1 */ outb 111 bsp/boot/ppc/prep/debug.c outb(COM_MCR, 0x03); /* Ready */ outb 112 bsp/boot/ppc/prep/debug.c outb(COM_FCR, 0x00); /* Disable FIFO */ outb 33 bsp/boot/x86/pc/debug.c extern void outb(int, u_char); outb 67 bsp/boot/x86/pc/debug.c outb(COM_THR, c); outb 75 bsp/boot/x86/pc/debug.c outb(0xe9, (u_char)c); outb 93 bsp/boot/x86/pc/debug.c outb(COM_IER, 0x00); /* Disable interrupt */ outb 94 bsp/boot/x86/pc/debug.c outb(COM_LCR, 0x80); /* Access baud rate */ outb 95 bsp/boot/x86/pc/debug.c outb(COM_DLL, 0x01); /* 115200 baud */ outb 96 bsp/boot/x86/pc/debug.c outb(COM_DLM, 0x00); outb 97 bsp/boot/x86/pc/debug.c outb(COM_LCR, 0x03); /* N, 8, 1 */ outb 98 bsp/boot/x86/pc/debug.c outb(COM_MCR, 0x03); /* Ready */ outb 99 bsp/boot/x86/pc/debug.c outb(COM_FCR, 0x00); /* Disable FIFO */ outb 88 bsp/hal/ppc/include/cpu.h void outb(int, u_char); outb 36 bsp/hal/ppc/include/io.h void outb(int, u_char); outb 51 bsp/hal/ppc/prep/diag.c outb(COM_THR, c); outb 83 bsp/hal/ppc/prep/diag.c outb(0xf00, (u_char)*str++); outb 78 bsp/hal/ppc/prep/interrupt.c outb(PIC_M + 1, mask & 0xff); outb 79 bsp/hal/ppc/prep/interrupt.c outb(PIC_S + 1, mask >> 8); outb 144 bsp/hal/ppc/prep/interrupt.c outb(port, val); outb 156 bsp/hal/ppc/prep/interrupt.c outb(PIC_M, 0x0c); /* poll and ack */ outb 159 bsp/hal/ppc/prep/interrupt.c outb(PIC_S, 0x0c); outb 223 bsp/hal/ppc/prep/interrupt.c outb(PIC_M, 0x11); /* Start initialization edge, master */ outb 224 bsp/hal/ppc/prep/interrupt.c outb(PIC_M + 1, 0x00); /* Set h/w vector = 0x0 */ outb 225 bsp/hal/ppc/prep/interrupt.c outb(PIC_M + 1, 0x04); /* Chain to slave (IRQ2) */ outb 226 bsp/hal/ppc/prep/interrupt.c outb(PIC_M + 1, 0x01); /* 8086 mode */ outb 228 bsp/hal/ppc/prep/interrupt.c outb(PIC_S, 0x11); /* Start initialization edge, master */ outb 229 bsp/hal/ppc/prep/interrupt.c outb(PIC_S + 1, 0x08); /* Set h/w vector = 0x8 */ outb 230 bsp/hal/ppc/prep/interrupt.c outb(PIC_S + 1, 0x02); /* Slave (cascade) */ outb 231 bsp/hal/ppc/prep/interrupt.c outb(PIC_S + 1, 0x01); /* 8086 mode */ outb 233 bsp/hal/ppc/prep/interrupt.c outb(PIC_S, 0x0b); /* Read ISR by default */ outb 234 bsp/hal/ppc/prep/interrupt.c outb(PIC_M, 0x0b); /* Read ISR by default */ outb 236 bsp/hal/ppc/prep/interrupt.c outb(PIC_S + 1, 0xff); /* Mask all */ outb 237 bsp/hal/ppc/prep/interrupt.c outb(PIC_M + 1, 0xfb); /* Mask all except IRQ2 (cascade) */ outb 90 bsp/hal/ppc/prep/machdep.c outb(0x92, val); outb 94 bsp/hal/ppc/prep/machdep.c outb(0x92, val); outb 46 bsp/hal/x86/include/cpufunc.h void outb(int, u_char); outb 66 bsp/hal/x86/pc/diag.c outb(VID_PORT, 0x0e); outb 67 bsp/hal/x86/pc/diag.c outb(VID_PORT + 1, (u_int)pos >> 8); outb 69 bsp/hal/x86/pc/diag.c outb(VID_PORT, 0x0f); outb 70 bsp/hal/x86/pc/diag.c outb(VID_PORT + 1, (u_int)pos & 0xff); outb 145 bsp/hal/x86/pc/diag.c outb(0xe9, (u_char)c); outb 179 bsp/hal/x86/pc/diag.c outb(COM_THR, c); outb 76 bsp/hal/x86/pc/interrupt.c outb(PIC_M + 1, mask & 0xff); outb 77 bsp/hal/x86/pc/interrupt.c outb(PIC_S + 1, mask >> 8); outb 142 bsp/hal/x86/pc/interrupt.c outb(port, val); outb 170 bsp/hal/x86/pc/interrupt.c outb(PIC_S, 0x20); /* Non specific EOI to slave */ outb 171 bsp/hal/x86/pc/interrupt.c outb(PIC_M, 0x20); /* Non specific EOI to master */ outb 210 bsp/hal/x86/pc/interrupt.c outb(PIC_S + 1, 0xff); /* Mask all */ outb 211 bsp/hal/x86/pc/interrupt.c outb(PIC_M + 1, 0xfb); /* Mask all except IRQ2 (cascade) */ outb 83 bsp/hal/x86/pc/machdep.c outb(0x64, 0xfe); outb 85 bsp/hal/x86/pc/machdep.c outb(0x80, 0);