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root/bsp/hal/arm/integrator/clock.c/* [<][>][^][v][top][bottom][index][help] */DEFINITIONSThis source file includes following definitions.1 /*- 2 * Copyright (c) 2008, Kohsuke Ohtani 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * clock.c - clock driver 32 */ 33 34 #include <kernel.h> 35 #include <timer.h> 36 #include <irq.h> 37 #include <cpufunc.h> 38 #include <sys/ipl.h> 39 40 #include "platform.h" 41 42 /* Interrupt vector for timer (TMR1) */ 43 #define CLOCK_IRQ 6 44 45 /* The clock rate per second - 1Mhz */ 46 #define CLOCK_RATE 1000000L 47 48 /* The initial counter value */ 49 #define TIMER_COUNT (CLOCK_RATE / HZ) 50 51 /* Timer 1 registers */ 52 #define TMR_LOAD (*(volatile uint32_t *)(TIMER_BASE + 0x100)) 53 #define TMR_VAL (*(volatile uint32_t *)(TIMER_BASE + 0x104)) 54 #define TMR_CTRL (*(volatile uint32_t *)(TIMER_BASE + 0x108)) 55 #define TMR_CLR (*(volatile uint32_t *)(TIMER_BASE + 0x10c)) 56 57 /* Timer control register */ 58 #define TCTRL_DISABLE 0x00 59 #define TCTRL_ENABLE 0x80 60 #define TCTRL_PERIODIC 0x40 61 #define TCTRL_INTEN 0x20 62 #define TCTRL_SCALE256 0x08 63 #define TCTRL_SCALE16 0x04 64 #define TCTRL_32BIT 0x02 65 #define TCTRL_ONESHOT 0x01 66 67 /* 68 * Clock interrupt service routine. 69 * No H/W reprogram is required. 70 */ 71 static int 72 clock_isr(void *arg) 73 { 74 75 splhigh(); 76 timer_handler(); 77 TMR_CLR = 0x01; /* Clear timer interrupt */ 78 spl0(); 79 return INT_DONE; 80 } 81 82 /* 83 * Initialize clock H/W chip. 84 * Setup clock tick rate and install clock ISR. 85 */ 86 void 87 clock_init(void) 88 { 89 irq_t clock_irq; 90 91 /* Setup counter value */ 92 TMR_CTRL = TCTRL_DISABLE; 93 TMR_LOAD = TIMER_COUNT; 94 TMR_CTRL |= (TCTRL_ENABLE | TCTRL_PERIODIC); 95 96 /* Install ISR */ 97 clock_irq = irq_attach(CLOCK_IRQ, IPL_CLOCK, 0, &clock_isr, 98 IST_NONE, NULL); 99 100 /* Enable timer interrupt */ 101 TMR_CTRL |= TCTRL_INTEN; 102 103 DPRINTF(("Clock rate: %d ticks/sec\n", CONFIG_HZ)); 104 } /* [<][>][^][v][top][bottom][index][help] */ | |||
Copyright© 2005-2009 Kohsuke Ohtani |