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root/bsp/drv/dev/input/i8042.h/* [<][>][^][v][top][bottom][index][help] */INCLUDED FROM1 /* 2 * Copyright (c) 2005, Kohsuke Ohtani 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _KMC_H 31 #define _KMC_H 32 /* 33 * i8042 Keyboard Mouse Controller definition 34 */ 35 36 /* I/O ports */ 37 #define KMC_DATA 0x60 38 #define KMC_PORTB 0x61 39 #define KMC_CMD 0x64 40 #define KMC_STS 0x64 41 42 /* Status */ 43 #define STS_PERR 0x80 /* Parity error */ 44 #define STS_TMO 0x40 /* Timeout */ 45 #define STS_AUXOBF 0x20 /* Mouse OBF */ 46 #define STS_INH 0x10 /* 0: inhibit 1: no-inhibit */ 47 #define STS_SYS 0x04 /* 0: power up 1:Init comp */ 48 #define STS_IBF 0x02 /* Input (to kbd) buffer full */ 49 #define STS_OBF 0x01 /* Output (from kbd) buffer full */ 50 51 /* Command */ 52 #define CMD_READ_CMD 0x20 53 #define CMD_WRITE_CMD 0x60 54 #define CMD_AUX_DIS 0xa7 55 #define CMD_AUX_EN 0xa8 56 #define CMD_KBD_DIS 0xad 57 #define CMD_KBD_EN 0xae 58 #define CMD_READ_OPORT 0xd0 59 #define CMD_WRITE_OPORT 0xd1 60 #define CMD_WRITE_AUX 0xd4 61 62 /* Auxillary device command */ 63 #define AUX_ENABLE 0xf4 64 #define AUX_DISABLE 0xf5 65 #define AUX_RESET 0xff 66 67 /* 68 * wait_obf: Wait output buffer full 69 * wait_obe: Wait input buffer empty 70 * wait_ibf: Wait input buffer full 71 * wait_ibe: Wait input buffer empty 72 */ 73 #define kmc_wait_obf() while ((bus_read_8(KMC_STS) & STS_OBF) == 0) 74 #define kmc_wait_obe() while (bus_read_8(KMC_STS) & STS_OBF) 75 #define kmc_wait_ibf() while ((bus_read_8(KMC_STS) & STS_IBF) == 0) 76 #define kmc_wait_ibe() while (bus_read_8(KMC_STS) & STS_IBF) 77 78 #endif /* !_KMC_H */ /* [<][>][^][v][top][bottom][index][help] */ | |||
Copyright© 2005-2009 Kohsuke Ohtani |