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   1 /*-
   2  * Copyright (c) 2005-2008, Kohsuke Ohtani
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. Neither the name of the author nor the names of any co-contributors
  14  *    may be used to endorse or promote products derived from this software
  15  *    without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  */
  30 #ifndef _ARM_CPU_H
  31 #define _ARM_CPU_H
  33 /*
  34  * Processor Status Register
  35  */
  36 #define PSR_MODE        0x0000001f
  37 #define PSR_USR_MODE    0x00000010
  38 #define PSR_FIQ_MODE    0x00000011
  39 #define PSR_IRQ_MODE    0x00000012
  40 #define PSR_SVC_MODE    0x00000013
  41 #define PSR_ABT_MODE    0x00000017
  42 #define PSR_UND_MODE    0x0000001b
  43 #define PSR_SYS_MODE    0x0000001f
  45 #define PSR_THUMB       0x00000020
  47 #define PSR_INT_MASK    0x000000c0
  48 #define PSR_FIQ_DIS     0x00000040
  49 #define PSR_IRQ_DIS     0x00000080
  51 #ifdef __gba__
  52 #define PSR_APP_MODE    PSR_SYS_MODE
  53 #else
  54 #define PSR_APP_MODE    PSR_USR_MODE
  55 #endif
  57 /*
  58  * Contorl register CP15 register 1
  59  */
  60 #define CTL_MMU         0x000000001     /* M: MMU/Protection unit enable */
  61 #define CTL_AFLT        0x000000002     /* A: Alignment fault enable */
  62 #define CTL_CACHE       0x000000004     /* C: Cache enable */
  63 #define CTL_WBUF        0x000000008     /* W: Write buffer enable */
  64 #define CTL_32BP        0x000000010     /* P: 32-bit exception handlers */
  65 #define CTL_32BD        0x000000020     /* D: 32-bit addressing */
  66 #define CTL_LABT        0x000000040     /* L: Late abort enable */
  67 #define CTL_BIGEND      0x000000080     /* B: Big-endian mode */
  68 #define CTL_SYSP        0x000000100     /* S: System protection bit */
  69 #define CTL_ROMP        0x000000200     /* R: ROM protection bit */
  70 #define CTL_BPRD        0x000000800     /* Z: Branch prediction enable */
  71 #define CTL_ICACHE      0x000001000     /* I: Instruction cache enable */
  72 #define CTL_HIVEC       0x000002000     /* V: Vector relocation */
  74 #define CTL_DEFAULT     (CTL_32BP | CTL_32BD | CTL_LABT)
  76 #ifndef __ASSEMBLY__
__BEGIN_DECLS
  79 void     cpu_init(void);
__END_DECLS
  82 #endif /* !__ASSEMBLY__ */
  83 #endif /* !_ARM_CPU_H */