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root/bsp/hal/arm/include/context.h/* [<][>][^][v][top][bottom][index][help] */INCLUDED FROM1 /*- 2 * Copyright (c) 2005-2009, Kohsuke Ohtani 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _ARM_CONTEXT_H 31 #define _ARM_CONTEXT_H 32 33 #ifndef __ASSEMBLY__ 34 #include <sys/types.h> 35 36 /** 37 * ARM register reference: 38 * 39 * Name Number ARM Procedure Calling Standard Role 40 * 41 * a1 r0 argument 1 / integer result / scratch register / argc 42 * a2 r1 argument 2 / scratch register / argv 43 * a3 r2 argument 3 / scratch register / envp 44 * a4 r3 argument 4 / scratch register 45 * v1 r4 register variable 46 * v2 r5 register variable 47 * v3 r6 register variable 48 * v4 r7 register variable 49 * v5 r8 register variable 50 * sb/v6 r9 static base / register variable 51 * sl/v7 r10 stack limit / stack chunk handle / reg. variable 52 * fp r11 frame pointer 53 * ip r12 scratch register / new-sb in inter-link-unit calls 54 * sp r13 lower end of current stack frame 55 * lr r14 link address / scratch register 56 * pc r15 program counter 57 */ 58 59 /* 60 * Common register frame for trap/interrupt. 61 * These cpu state are saved into top of the kernel stack in 62 * trap/interrupt entries. Since the arguments of system calls are 63 * passed via registers, the system call library is completely 64 * dependent on this register format. 65 */ 66 struct cpu_regs { 67 uint32_t r0; /* +0 (00) */ 68 uint32_t r1; /* +4 (04) */ 69 uint32_t r2; /* +8 (08) */ 70 uint32_t r3; /* +12 (0C) */ 71 uint32_t r4; /* +16 (10) */ 72 uint32_t r5; /* +20 (14) */ 73 uint32_t r6; /* +24 (18) */ 74 uint32_t r7; /* +28 (1C) */ 75 uint32_t r8; /* +32 (20) */ 76 uint32_t r9; /* +36 (24) */ 77 uint32_t r10; /* +40 (28) */ 78 uint32_t r11; /* +44 (2C) */ 79 uint32_t r12; /* +48 (30) */ 80 uint32_t sp; /* +52 (34) */ 81 uint32_t lr; /* +56 (38) */ 82 uint32_t cpsr; /* +60 (3C) */ 83 uint32_t svc_sp; /* +64 (40) */ 84 uint32_t svc_lr; /* +68 (44) */ 85 uint32_t pc; /* +72 (48) */ 86 }; 87 88 /* 89 * Kernel mode context for context switching. 90 */ 91 struct kern_regs { 92 uint32_t r4; 93 uint32_t r5; 94 uint32_t r6; 95 uint32_t r7; 96 uint32_t r8; 97 uint32_t r9; 98 uint32_t r10; 99 uint32_t r11; 100 uint32_t sp; 101 uint32_t lr; 102 }; 103 104 /* 105 * Processor context 106 */ 107 struct context { 108 struct kern_regs kregs; /* kernel mode registers */ 109 struct cpu_regs *uregs; /* user mode registers */ 110 struct cpu_regs *saved_regs; /* savecd user mode registers */ 111 }; 112 113 typedef struct context *context_t; /* context id */ 114 115 #endif /* !__ASSEMBLY__ */ 116 117 /* 118 * Register offset in cpu_regs 119 */ 120 #define REG_R0 0x00 121 #define REG_R1 0x04 122 #define REG_R2 0x08 123 #define REG_R3 0x0c 124 #define REG_R4 0x10 125 #define REG_R5 0x14 126 #define REG_R6 0x18 127 #define REG_R7 0x1c 128 #define REG_R8 0x20 129 #define REG_R9 0x24 130 #define REG_R10 0x28 131 #define REG_R11 0x2c 132 #define REG_R12 0x30 133 #define REG_SP 0x34 134 #define REG_LR 0x38 135 #define REG_CPSR 0x3c 136 #define REG_SVCSP 0x40 137 #define REG_SVCLR 0x44 138 #define REG_PC 0x48 139 140 #define CTXREGS (4*19) 141 142 #endif /* !_ARM_ARCH_H */ /* [<][>][^][v][top][bottom][index][help] */ | |||
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Copyright© 2005-2009 Kohsuke Ohtani |
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