bits              194 bsp/drv/dev/dma/i8237.c 	u_int chan, bits, mode;
bits              208 bsp/drv/dev/dma/i8237.c 	bits = (chan < 4) ? chan : chan >> 2;
bits              212 bsp/drv/dev/dma/i8237.c 	bus_write_8(regs->mask, bits | 0x04);	/* Disable channel */
bits              214 bsp/drv/dev/dma/i8237.c 	bus_write_8(regs->mode, bits | mode);	/* Set mode */
bits              221 bsp/drv/dev/dma/i8237.c 	bus_write_8(regs->mask, bits);		/* Enable channel */
bits              231 bsp/drv/dev/dma/i8237.c 	u_int bits;
bits              238 bsp/drv/dev/dma/i8237.c 	bits = (chan < 4) ? chan : chan >> 2;
bits              239 bsp/drv/dev/dma/i8237.c 	bus_write_8(dma_regs[chan].mask, bits | 0x04);	/* Disable channel */
bits              165 bsp/hal/arm/gba/interrupt.c 	uint16_t bits;
bits              168 bsp/hal/arm/gba/interrupt.c 	bits = ICU_IF;
bits              171 bsp/hal/arm/gba/interrupt.c 		if (bits & (uint16_t)(1 << vector))
bits              183 bsp/hal/arm/gba/interrupt.c 	bits = ICU_IF;
bits              184 bsp/hal/arm/gba/interrupt.c 	if (bits & IRQ_VALID)
bits              136 bsp/hal/arm/integrator/interrupt.c 	uint32_t bits;
bits              140 bsp/hal/arm/integrator/interrupt.c 	bits = ICU_IRQSTS;
bits              142 bsp/hal/arm/integrator/interrupt.c 		if (bits & (uint32_t)(1 << vector))